MODELING FINFETS, NANOWIRES AND NANOSHEETS

The transition from two-dimensional (2D) transistors to three-dimensional (3D) transistors at the beginning of the 21st century required the development of new models for 3D transistors. The work of developing models of semiconductor devices is a typical activity of the Academy, which our group followed, beginning the development of a new model for 3D FinFET devices, in 2006. These devices have a silicon fin, surrounded by three gates, two laterals and one on the top. The Si layer is narrow enough, creating a potential distribution across its thickness, where the potential at the center is different from zero. Considering this potential distribution and the fact that the Si layer is doped, lead to a transcendental equation for the distribution of the electric field from gate to gate, that has no direct analytical solution.
In this presentation we will show an example of a compact, continuous and analytical model known as Symmetric Doped Double-Gate Model (SDDGM), where the indicate problems were solved. The model was complemented with variable mobility, the effects of short channel, leakage currents and dependence on ambient temperature. In addition, it was demonstrated that this model can be used to model also recent 3D structures, such as nanowires, nanosheets and stacked nanosheets. Validation of the using this model for these new devices will be shown. SDDGM was implemented in the circuit simulator SmartSPICE, using Verilog-A language.
Even today, the development of more precise models, as well as complements for applying them to new devices, is an open topic for the Academy.
Co-sponsored by: Centro Universitario FEI
Speaker(s): Dr. Antonio Cerdeira,
Centro Universitario FEI, Av. Humberto de A. C. Branco, 3972, Sao Bernardo do Campo, Sao Paulo, Brazil, 09850901