Data: 31 de agosto de 2023 as 14:00 horas
Endereço: Museu de Arte do Rio – MAR, Praça Mauá, 5 – Centro, Rio de Janeiro – RJ, 20081-240

O capítulo IEEE CASS Rio convida seus membros para participar do IEEE CASS Workshop: Current Trends in IC Design, o qual acontecerá no Museu de Arte do Rio (MAR) no dia 31 de agosto a partir das 14:00 horas. O Workshop acontecerá como um co-evento do SBCCI – Chip in Rio 2023, a principal conferência de microeletrônica do Brasil. Os membros ativos da IEEE CAS Society previamente inscritos até dia 22/08, e os participantes da conferencia Chip in Rio, terão o acesso gratuito ao Workshop.

Lecture 01: Ratio based analog/RF design: a generalization of gm/ID and Inversion Coefficient methods – By Fernando Silveira – 14:20 PM to 15:00 PM

Abstract

Design methods for analog integrated circuits based on gm/ID have the key feature of being based on a magnitude (the gm/ID ratio) that provides information about the transistor operation independently of its width (W, letting aside very narrow transistors rarely applied in analog design) and length (L), except for a slight dependence on L in short channel devices. A general characteristic for the transistors of a given length in a given process is obtained. Therefore, it gives a global view and orientation about the design space. This makes it very suitable for helping the designer to gain insight on how to tune the design and, particularly, aiding novel designers to quickly find their way in the analog design art. The same applies to the, somehow “dual”, inversion coefficient (IC) based methods. Both methods are based on magnitudes (gm/ID and IC) that are ratios (or proportional to ratios) of key magnitudes of the transistor operation. Extensions and evolutions of the gm/ID method have, implicitly or explicitly, identified this “ratio based characteristic” and have shown the advantages of considering other key ratios of magnitudes that share the same characteristics as gm/ID of being W independent. The approach presented is particularly appropriate for nanoscale devices where multiple unitary devices in parallel are usually applied.  This talk will provide an overview on these ratio based analog design approaches, contributing to show a general vision about them. These methods originally targeted small signal analog design. In the talk it will be shown examples of extension of the basic idea to nonlinear RF blocks (power amplifiers and envelope detectors) as well as to distortion analysis.

Biography

Fernando Silveira received the electrical engineering degree from Universidad de la República, Montevideo, Uruguay, in 1990, and the M.Sc. and Ph.D. degrees in microelectronics from Université catholique de Louvain, Louvain-la-Neuve, Belgium, in 1995 and 2002, respectively. He is currently a Professor with the Electrical Engineering Department, Universidad de la República. His research interests include the design of ultra-low-power analog and RF integrated circuits and systems, in particular with biomedical application. In this field, he has co-authored two books and many technical papers. He has had multiple industrial activities including leading the design of an application specified integrated circuit for implantable pacemakers and designing analog circuit modules for implantable devices for various companies worldwide, field in which he continues to do consulting. He was member of the Technical Advisory Board of Gtronix, Inc, USA from 2006 to 2010, received the “Ingeniero Destacado” (Distinguished Engineer) award by the Uruguayan Association of Engineers in 2007 and was a member for 2011-2012 of the Distinguished Lecturers Program of the IEEE Circuits and Systems Society. Since 2017 he is a member of the Honorary Committee of the National Researchers System of Uruguay.

Lecture 02: Physical Design: New Solutions Inspired in the Past – By Ricardo Reis – 15:00 PM to 15:40 PM

Abstract

By the end of years ‘70s, microprocessors were designed by hand, showing na excellent layout compaction. It will be presented some highlights of the reverse engineering of the Z8000, which control part was designed by hand, showing several layout optimization strategies as well an optimization of the number of transistors. The observation of the Z8000 layout inspired the research of methods to do the automatic generation of the layout of any transistor network, allowing to reduce the number of transistors to implement a circuit, and by consequence, the leakage power consumption. Power Optimization is a keyword in the IoT world. Some of the layout automation tools developed by our group are briefly presented. It will also be presented why the use of visualization tools can help to improve the quality of EDA tools and to improve the quality of the solution.

Biography

Ricardo Reis received a Bachelor degree in Electrical Engineering from Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil, in 1978, and a Ph.D. degree in Microelectronics from the National Polytechnic Institute of Grenoble (INPG), France, in 1983. Doctor Honoris Causa by the University of Montpellier in 2016. He is a full professor at the Informatics Institute of Federal University of Rio Grande do Sul. His main research includes physical design automation, design methodologies, fault tolerant systems and microelectronics education. He has more than 700 publications including books, journals and conference proceedings. He was vice-president of IFIP (International Federation for Information Processing) and he was also president of the Brazilian Computer Society (two terms) and vice-president of the Brazilian Microelectronics Society. He is an active member of CASS and he received the 2015 IEEE CASS Meritorious Service Award. He was vice-president of CASS for two terms (2008/2011). He is the founder of the Rio Grande do Sul CAS Chapter, which got the World CASS Chapter of The Year Award 2011, 2012, 2018 and 2022, and R9 Chapter of The Year 2013, 2014, 2016, 2017 and 2020. He is a founder of several conferences like SBCCI and LASCAS, the CASS Flagship Conference in Region 9. He was the General or Program Chair of several conferences like IEEE ISVLSI, SBCCI, IFIP VLSI-SoC, ICECS, PATMOS. Ricardo was the Chair of the IFIP/IEEE VLSI-SoC Steering Committee, vice-chair of the IFIP WG10.5 and he is Chair of IFIP TC10. He also started with the EMicro, an annually microelectronics school in South Brazil. In 2002 he received the Researcher of the Year Award in the state of Rio Grande do Sul. He is a founding member of the SBC (Brazilian Computer Society) and also founding member of SBMicro (Brazilian Microelectronics Society). He was member of CASS DLP Program (2014/2015), and he has done more than 70 invited talks in conferences. Member of IEEE CASS BoG and IEEE CEDA BoG. He is the CASS representative at the IEEE IoT TC. Ricardo received the IFIP Fellow Award in 2021 and the ACM/ISPD Lifetime Achievement Award in 2022. He received the 2023 IEEE CASS John Choma Educational Award.

Lecture 03: The Tangled Tree of Technology – by Victor Grimblatt – 15:40 PM to 16:20 PM

Abstract

Charles Darwin’s “tree of life” is a model used to represent the “vertical evolution”: in Darwin’s “tree of life”, each new generation inherits the parental genes, the strongest, most favorable genes sprout, while the weakest become extinct. There is a “tree of technology” too. In truth, there are many; among the most notable are CMOS, and xPU. In these “trees of technology”, each new generation inherits the parental “genes”, unchanged, unchallenged, just smaller (CMOS) or bigger (xPU), an artificial Galapagos Islands ecosystem. Darwin’s “tree of life” has been challenged by UIUC Prof. Carl Woese, an “evolutionary biologist”, who proposed a more “tangled tree of life”, in which gene transfer, and therefore evolution happens both vertically (VGT), slowly, generation after generation of one organism, and horizontally (HGT), rapidly, across [even radically] different organisms. Over the last four billion years, there have been several bursts of horizontal evolution, among which the “Cambrian explosion”, when practically all major phyla started appearing in the fossil record. In this talk, I propose that we are at the dawn of a technological “Cambrian explosion”; that we must challenge the established “trees of technology”; that only the entanglement of many [even radically] different “trees of technology” will allow us to leapfrog the fundamental, physical limits that CMOS and xPU, are hitting against.

Biography

Victor Grimblatt has an engineering diploma in microelectronics from Institut Nationale Polytechnique de Grenoble (INPG – France) and an electronic engineering diploma from Universidad Tecnica Federico Santa Maria (Chile).  He got his PhD on Electronics in 2021 from University of Bordeaux. He is currently R&D Group Director and General Manager of Synopsys Chile. He has published several papers in IoT, EDA, Smart Agriculture, Climate Change, and embedded systems development. Since 2012 he is chair of the IEEE Chilean joint chapter of CASS/EDS/SSCS. He has been part of several conferences TCP (ISCAS, ICECS, LASCAS) and Steering Committees. He is TPC chair of ISCAS 2024. He is member of the IEEE CASS Board of Governors for the period 2021 – 2023. He founded the Electronics for Agrifood SIG at CASS and chairs it. He was Chair of LASCAS Steering Committee from 2018 to 2022. He is CASS representative at the IEEE Climate Change TAB. He was President of the Chilean Electronic and Electrical Industry Association (AIE) from 2017 to 2021. From 2006 to 2008 he was member of the “Chilean Offshoring Committee” organized by the Minister of Economy of Chile. In 2010 he was awarded as “Innovator of the Year in Services Export”. In 2022 he was awarded as “IEEE/AIE Best Engineer” in Chile. In 2023 he was awarded as IEEE R9 Outstanding Engineer”. Victor’s research areas are EDA (Electronic Design Automation), Climate Change, and Smart Agriculture.