¡Aprende SolidWorks desde cero! 🛠✨ ¿Te interesa el diseño en 3D y quieres dominar una de las herramientas más poderosas del mercado? Únete a nuestro *Curso de SolidWorks para Principiantes* y da tus primeros pasos en el mundo del modelado 3D. 🔹 ¿Qué aprenderás? - Principios básicos del modelado en 3D - Creación de piezas y ensamblajes - interpretación de planos - Consejos y trucos para optimizar tu trabajo No necesitas experiencia previa, ¡solo ganas de aprender! 🚀 *Cupo limitado*, ¡inscríbete ya! 📩 Para más información y registro: https://forms.gle/39yPQMeK5s71Ez4f9 [] Avenida Tecnológico #1500, Col. Lomas de Santiaguito, Morelia, Michoacan de Ocampo, Mexico, 58120

¡Aprende SolidWorks desde cero! 🛠✨ ¿Te interesa el diseño en 3D y quieres dominar una de las herramientas más poderosas del mercado? Únete a nuestro *Curso de SolidWorks para Principiantes* y da tus primeros pasos en el mundo del modelado 3D. 🔹 ¿Qué aprenderás? - Principios básicos del modelado en 3D - Creación de piezas y ensamblajes - interpretación de planos - Consejos y trucos para optimizar tu trabajo No necesitas experiencia previa, ¡solo ganas de aprender! 🚀 *Cupo limitado*, ¡inscríbete ya! 📩 Para más información y registro: https://forms.gle/39yPQMeK5s71Ez4f9 [] Avenida Tecnológico #1500, Col. Lomas de Santiaguito, Morelia, Michoacan de Ocampo, Mexico, 58120

Unlike the other propose courses this would be a beginner course that some IEEE members will teach to High School students. Besides teaching some of the knowledge that they have gathered through their time in the University, they are going to learn the skill to talk in front of many people and to be patient with the students that are just going to learn about Arduino. Morelia, Michoacan de Ocampo, Mexico

This course is made for beginners who are interested in creating their first 3D models by their own. They are going to learn how to use the software properly and some tips that will help them to use SolidWorks more easily. Morelia, Michoacan de Ocampo, Mexico

Segundo Otoño de Diseño Electronico Este curso ofrece una introducción integral al diseño y fabricación de circuitos impresos (PCBs), enfocado tanto en principiantes como en personas con experiencia básica en electrónica. A lo largo del curso, los participantes aprenderán los principios fundamentales del diseño de PCBs utilizando software especializado ( Altium Designer ), desde la captura esquemática hasta la creación de diseños avanzados para múltiples capas. El curso abarca todas las fases del proceso, desde la selección de componentes y el ruteo de señales hasta las técnicas de fabricación, prototipado y pruebas. Los estudiantes tendrán la oportunidad de aplicar sus conocimientos en proyectos prácticos, desarrollando sus propias PCBs, y aprenderán sobre diferentes métodos de producción, desde la fabricación casera hasta la manufactura en masa. Para poder utilizar el software durante el evento es necesario que todos los asistentes consulten previamente el siguiente enlace: - https://www.youtube.com/watch?v=zjrceOWiDLM [] Co-sponsored by: Departamento de Ingeniería Eléctrica, Sección Bioelectronica, Cinvestav. Speaker(s): Gibram, Abraham Agenda: Bldg: Aula Joaquín Remolina, Sección Bioelectronica, Av Instituto Politécnico Nacional 2508, San Pedro Zacatenco, Gustavo A. Madero, Ciudad de México, CDMX, Ciudad de Mexico, Distrito Federal, Mexico, 07360

Artemis: "A Journey from Apollo to the Future of Space Exploration" is a captivating webinar series that explores the evolution of human space exploration from the historic Apollo missions to NASA's groundbreaking Artemis program. Scheduled to take place from October 16 to October 19, 2024, this event will provide participants with an in-depth understanding of the technological advancements, mission goals, and future prospects that are shaping the next era of space exploration. Organized as a collaboration between IEEE AESS ENSIT SBC and AESS UPIITA of Rama Estudiantil, the event will feature four sessions, each offering insights into key aspects of space exploration. Attendees will have the opportunity to learn from leading experts in the field and gain a comprehensive overview of the legacy of Apollo, the evolution of space technology, the objectives of the Artemis program, and the future of human space exploration beyond Artemis. The sessions will be held on Zoom, with registration required for each individual session. Participants will receive a unique Zoom link via email upon registration. Don't miss this opportunity to explore the past, present, and future of space exploration with this exciting and educational event. Virtual: https://events.vtools.ieee.org/m/432734

Abstract: DRAM standards have evolved tremendously over the last two-and-a-half decades, leading to diversification not only in the architecture of the memory array but also in that of the off-chip interface. Application-specific signaling channels have influenced the transceiver design nearly as much as system power and bandwidth requirements have. The influence of the multi-drop server channel, along with a broad range of target environments, has led the DDR branch of JEDEC DRAMs to incorporate multi-tap Decision Feedback Equalization to maximize flexibility, while shrinking supply voltages to facilitate energy reduction have led Low-Power DDR (LPDDR) to completely rethink the output driver structure. In parallel, Graphics DDR (GDDR) has reached speeds requiring nearly equal care of the external channel and the chip itself. The adoption of multi-level signaling in GDDR6x and GDDR7 to relax on-chip frequency requirements has only heightened the need for more rigorous co-design of transceiver, package and system characteristics. And, of course, the integration of silicon interposers to support High Bandwidth Memory (HBM) has driven a paradigm shift in memory interface design. With all of these adaptations, and many others not captured here, the splintering DRAM family continues to push the boundaries of single-ended signaling into the future.† This presentation briefly explores what has driven the diversification in DRAM signaling schemes over the decades, will discuss the motivation behind present embodiments, and will project into the future to where the DRAM interface is likely headed (e.g., features and functions necessary for continued energy-efficient bandwidth scaling). Speaker(s): Dr. Timithy (Tim) Hollis Agenda: Agenda: Presentation Break Presentation Clousure CINVESTAV Unidad Guadalajara, Av. del Bosque 1145, El Bajío, Zapopan, Jalisco, Mexico, 45017

Abstract: DRAM standards have evolved tremendously over the last two-and-a-half decades, leading to diversification not only in the architecture of the memory array but also in that of the off-chip interface. Application-specific signaling channels have influenced the transceiver design nearly as much as system power and bandwidth requirements have. The influence of the multi-drop server channel, along with a broad range of target environments, has led the DDR branch of JEDEC DRAMs to incorporate multi-tap Decision Feedback Equalization to maximize flexibility, while shrinking supply voltages to facilitate energy reduction have led Low-Power DDR (LPDDR) to completely rethink the output driver structure. In parallel, Graphics DDR (GDDR) has reached speeds requiring nearly equal care of the external channel and the chip itself. The adoption of multi-level signaling in GDDR6x and GDDR7 to relax on-chip frequency requirements has only heightened the need for more rigorous co-design of transceiver, package and system characteristics. And, of course, the integration of silicon interposers to support High Bandwidth Memory (HBM) has driven a paradigm shift in memory interface design. With all of these adaptations, and many others not captured here, the splintering DRAM family continues to push the boundaries of single-ended signaling into the future.† This presentation briefly explores what has driven the diversification in DRAM signaling schemes over the decades, will discuss the motivation behind present embodiments, and will project into the future to where the DRAM interface is likely headed (e.g., features and functions necessary for continued energy-efficient bandwidth scaling). Speaker(s): Dr. Timithy (Tim) Hollis Agenda: Agenda: Presentation Break Presentation Clousure Bldg: Auditorio Nikolai V. Mitskievich, Universidad de Guadalajara, CUCEI, Blvd. Gral. Marcelino García Barragán 1421, Olímpica, Guadalajara, Jalisco, Mexico, 44430