IEEE CASS Rio Chapter Lecture – Using Fault Tolerant RISC-V Processors and Fault Tolerant AI engines into FPGAs for Earth Observation and other High Reliable Applications

This talk presents recent advances in the design and deployment of fault-tolerant RISC-V processors and fault-tolerant AI engines implemented on SRAM-based FPGAs targeting Earth Observation and other mission-critical systems. The presentation discusses architectural and system-level techniques to mitigate soft errors, including modular and distributed redundancy, selective hardening, error detection and correction mechanisms, configuration memory scrubbing, and resilience-aware design methodologies. Particular emphasis is placed on open RISC-V soft-cores and AI accelerators for on-board inference, highlighting trade-offs between reliability, performance, power, and resource utilization.
Speaker(s): Fernanda Kastensmidt
Room: bloco H, sala 322, Centro de Tecnologia da UFRJ, Cidade Universitária, Centro de Tecnologia, Rio de Janeiro, Rio de Janeiro, Brazil, 21941972