EDS/SSC DLL – 2024 – Efficient Computing for AI and Robotics: From Hardware Accelerators to Algorithm Design

Invitation IEEE Joint Chapter No. 3 (EDS/SCC) of the Argentina Section invites you to the conference “PEfficient Computing for AI and Robotics: From Hardware Accelerators to Algorithm Design” given by the distinguished SSC IEEE speaker phd. Vivienne Sze from the Electrical Engineering and Computer Science Department at MIT. Please note that the talk is sponsored under the IEEE Electron Devices Society Distinguished Lecturers Program. Abstract The compute demands of AI and robotics continue to rise due to the rapidly growing volume of data to be processed; the increasingly complex algorithms for higher quality of results; and the demands for energy efficiency and real-time performance. In this talk, we will discuss the design of efficient hardware accelerators and the co-design of algorithms and hardware that reduce the energy consumption while delivering real-time and robust performance for applications including deep neural networks, data analytics with sparse tensor algebra, and autonomous navigation. We will also discuss our recent work that balances flexibility and efficiency for domain-specific accelerators and reduces the cost of analog-to-digital converters for processing-in-memory accelerators. Throughout the talk, we will highlight important design principles, methodologies, and tools that can facilitate an effective design process. Co-sponsored by: Universidad Tecnológica Nacional Facultad Regional Buenos aires – Departamento de Ingeniería Electrónica Speaker(s): phd. Vivienne Sze Room: Departamento de Electrónica, Universidad Tecnológica Nacional Facultad Regional Buenos Aires, Medrano 951 , CABA, Distrito Federal, Argentina